The present invention relates to the field of electrical integrated circuit testing. More particularly, the present invention relates to a scan test interface utilized to facilitate a system level scan test architecture.
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results include numerous printed circuit boards (PCBs) comprising a variety of microelectronic integrated circuits (ICs). Efficient and reliable system wide testing of ICs in an electronic system is critical in determining if a system operates properly and provides desired results.
The complexity of commonly used integrated circuits has advanced dramatically and built in self test (BIST) diagnostics capability is essential for effective circuit testing, debugging, and maintenance. Modern BIST techniques typically include the insertion of a scan test architecture in an IC to provide controllability and observability of IC components. Usually, scan test architectures include the ability to extract or insert state information to and from a number of devices within a system (e.g., a computer system) that conform to a scan testing specification. Scan testing of complex electronic systems and circuits often requires analysis of measurements taken or xe2x80x9ccapturedxe2x80x9d at numerous test points (e.g., appropriately selected circuit nodes) after the application of test vectors to stimulate certain aspects of a circuit (e.g., a NAND gate, OR gate, functional logic devices, etc.).
Scan test architectures usually include special signals that provide directions and test vectors for scan test operations. For example, an International Electrical and Electronic Engineering (IEEE) Standard 1149.1 (also referred to as Joint Task Action Group (JTAG)) boundary scan compliant architecture requires at least 4 signals to be dedicated to scan test operations.
The IEEE 1149.1 standard signals are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS). In addition JTAG IEEE 1149.1 boundary scan standard architectures often include other optional signals, such as a very common test reset (TRST) signal. Coordinating the communication of typical scan test signals (e.g., IEEE 1149.1 compliant signals) to a multitude of various destinations throughout a typical electronic system (e.g., test points, test controllers, test registers, etc.) often requires significant resources.
Traditional system level scan test architectures typically rely upon dedicated communication lines to communicate scan test signals. The dedicated scan test communication lines are often arranged in a star configuration in which scan test control signals are transmitted directly from a central controller to test points or PCB slots in the scan test system. Typically, each test point or PCB slot in a system requires a set of scan test control signals resulting in significant resources being expended on providing numerous dedicated lines for communication of scan test signals to each testing point or PCB slot. The numerous lines typically required in a star configuration also imposes significant limitations of the number of PCBs that are scanned in an individual module.
Traditional scan test systems also typically require the insertion of an external scan control PCB for system level scan control and signaling. These external scan control PCBs pose particular problems for module to module interconnect testing, often requiring additional resources to be expended designing and implementing a scan multiplexer box to direct scan operations at particular modules. Additionally, scan controller PCBs are usually difficult to physically install and remove since they are not typically part of a product design. Furthermore, a scan controller PCB is not usually controlled (e.g., reset) by an overall electronic system controller and thus causes additional problems when it is installed during normal operations.
In addition to requiring significant resources to be expended on providing numerous dedicated lines for scan test communications, traditional system level scan test architectures typically have other serious limitations and inconvenient idiosyncrasy that detract from desirable scan test control and observability functions. For example, typical system levels scan test architectures are usually limited to one scan test chain on each target PCB. This makes testing of PCBs that have scannable devices on subordinate (e.g., daughter) PCBs difficult, especially if the PCBs are reconfigured. Reconfiguring in a traditional system level scan test architecture is particularly problematic for most scan test tools because they usually require significant resources to program the software to cope with the large number of reconfiguration scenarios that are possible.
Additional difficulties are experienced in traditional system level scan test architecture systems that do not provide sufficient independent programmatic scan test control for subordinate scan test chains. Traditional systems often require different scan test chains to share key scan test signals (e.g., TCK, TMS, etc.). This makes autonomous or independent scan testing of subordinate scan test chains very difficult. It is also particularly difficult to implement in traditional systems comprising PCBs with scan test chains operating on different voltage domains. In these environments some of the scannable devices operate in one voltage domain while other scannable devices operate in another voltage domain. Most traditional scan test systems attempting to operate in electronic systems comprising multiple different voltage domains often require significant resources to be expended on multiple levels of voltage conversion to interface scan signals to and from various different ASICs operating in different voltage domains.
What is required is a system and method that facilitates efficient and effective scan testing on a system wide basis. The system and method should facilitate flexible configuration and communication of scan test signals between a system scan test controller and a scan test target device. The system and method should also assist communication of scan test control signals to subordinate scan test chains. The system and method should facilitate scan testing of PCBs comprising scannable ICs that operate in different voltage domains.
Accordingly, the present invention is a scan test interface system and method that facilitates efficient and effective scan testing on a system wide basis. The present invention provides a scan test signal interface between an upstream scan test device and downstream scan test devices. The system and method of the present invention includes a scan test interface that facilitates flexible configuration and communication of scan test signals between a between a system scan test controller and a scan test target device (e.g., scannable devices included on a PCB). A scan test interface of the present invention also assists independent communication of scan test signals to subordinate scan test chains. Furthermore, the system and method of the present invention facilitates scan testing of PCBs comprising scannable ICs that operating in different voltage domains.
One embodiment of a present invention includes a scan interface chip (SIC) that acts as a communication interface. The SIC provides a complete set of JTAG scan test signals between a system controller and multiple different scan test chains. In one exemplary implementation of the present invention, one of the scan test chains comprises devices operating in a different voltage and clock domains from devices included in another scan test chain. In one embodiment of the present invention, the SIC comprises a system interface, a scan test interface controller, a scan test interface register, and a selection circuit. One embodiment of the SIC includes a number in can (NIC) circuit. One embodiment of a SIC board interface includes multiple scan test chain ports and each set of scan test chain ports provides a complete set of scan test signals for each scan test chain a SIC services. In one embodiment of a SIC of the present invention, scan test signals are xe2x80x9ccopiedxe2x80x9d and transmitted to downstream devices included in different scan test chains. The SIC then concatenates returning scan test signals (e.g., from downstream devices) from the multiple scan test chains back together in a manner that xe2x80x9cconvertsxe2x80x9d differing voltage levels and enables scan test software to treat downstream devices serviced by the SIC as one scan test chain. Supporting multiple scan test chains also facilitates PCB reconfiguration (including daughter boards) into separate scan test chains in a manner that reduces problems associated with tracking numerous configuration combinations.